1. Field of the Invention
The present invention relates to a single-ended sense amplifier circuit amplifying a signal read out from a memory cell and transmitted through a bit line, and to a semiconductor memory device having the single-ended amplifier circuit.
2. Description of Related Art
As capacity of semiconductor memory devices such as a DRAM has recently become large, it has become difficult to obtain a sufficient capacitance value of a capacitor included in a memory cell for the purpose of miniaturization of the memory cell. A charge transfer type sense amplifier circuit is conventionally known as a sense amplifier circuit suitable for amplifying a minute signal voltage readout from the memory cell. For example, configurations of a variety of charge transfer type sense amplifiers are disclosed in the following Patent References 1 to 4.    Patent Reference 1: Japanese Patent Application Laid-open No. 2000-195268    Patent Reference 2: Japanese Patent Application Laid-open No. 2002-157885    Patent Reference 3: Japanese Patent Application Laid-open No. H11-16384    Patent Reference 4: Japanese Patent Application Laid-open No. 2007-73121
FIG. 23 shows a configuration example of a conventional typical charge transfer type sense amplifier circuit. In FIG. 23, there are shown a memory cell MC composed of an N-type selection transistor Q0 and a capacitor Cs, two N-type MOS transistors Qg and Qp, and a latch type differential amplifier 100. The selection transistor Q0 has a source connected to a bit line BL, and a gate connected to a word line WL. The capacitor Cs is connected between the drain of the selection transistor Q0 and a ground potential. The MOS transistor Qg switches connection between the bit line BL and a sense node Ns in response to a control voltage Vg inputted to the gate of the MOS transistor Qg. The MOS transistor Qp switches connection between a power supply voltage VDD and the sense node Ns in response to a control signal SET inputted to the gate of the MOS transistor Qp. The latch type differential amplifier 100 receives a signal voltage at the sense node Ns and a reference voltage Vr respectively, and amplifies a difference therebetween and latches it. In addition, the reference voltage Vr is set to an intermediate voltage of the both voltages at the sense node Ns in reading out high and low level data from the memory cell MC.
In FIG. 23, a bit line capacitance Cb is formed at the bit line BL and a capacitance Ca is formed at the sense node Ns. It has been found from the study of the inventor that operation modes assumed in a sense amplifier circuit are determined depending on parameters such as the capacitance Cs of the capacitor, the potential of the bit line BL and the bit line capacitance Cb, and the potential of the sense node Ns and the capacitance Ca (refer to FIG. 1 and description thereof), and that the sense amplifier circuit is operated in accordance with later-mentioned formulas 1 to 3. It has been confirmed that a charge transfer mode is dominant in the conventional charge transfer type sense amplifier circuit shown in FIG. 23 among the above-mentioned operation modes.
However, when using the charge transfer type sense amplifier circuit of FIG. 23, it is inevitable that the capacitance Ca at the sense node Ns increases since the large-scale latch type differential amplifier 100 is employed. For example, in a configuration including 512 memory cells MC on one bit line BL, it is assumed that the capacitance Ca=10 fF at the sense node Ns is obtained for the bit line capacitance Cb=50 fF. As a result of the study of the inventor under such a condition, it has been found that the amplifying operation of the sense amplifier circuit is not hindered when the power supply voltage VDD is relatively high (for example, 3V or 2V), however, the amplifying operation is hindered when lowering the power supply voltage VDD, for example, an operation under VDD=1V (refer to FIGS. 5 and 6 and descriptions thereof). Under this condition, the voltage difference at the sense node Ns in reading out high and low level data from the memory cell MC becomes reduced, and sufficient operating margin cannot be obtained. Further, it has been found that such a tendency becomes further pronounced when using the capacitor Cs having a smaller capacitance to miniaturize the memory cell MC. As described above, the conventional charge transfer type sense amplifier circuit has a problem in that it is difficult to apply to the configuration achieving the lower voltage operation using memory cells MC having a small capacitance.